This section covers all columns in the Processor Table. Only a subset of these registers relate to the instruction set; the remaining registers exist only to enable an efficient arithmetization and are marked with an asterisk (*).

*clkcycle countercounts the number of cycles the program has been running for
*IsPaddingpadding indicatorindicates whether current state is only recorded to improve on STARK's computational runtime
*PreviousInstructionprevious instructionholds the opcode of the instruction executed in the previous clock cycle (or 0 if such cycle exists)
ipinstruction pointercontains the memory address (in Program Memory) of the instruction
cicurrent instruction registercontains the current instruction
nianext instruction registercontains either the instruction at the next address in Program Memory, or the argument for the current instruction
*ib0 through ib7instruction bitdecomposition of the instruction's opcode used to keep the AIR degree low
jspjump stack pointercontains the memory address (in jump stack memory) of the top of the jump stack
jsojump stack origincontains the value of the instruction pointer of the last call
jsdjump stack destinationcontains the argument of the last call
st0 through st15operational stack registerscontain explicit operational stack values
*ospoperational stack pointercontains the OpStack address of the top of the operational stack
*osvoperational stack valuecontains the (stack) memory value at the given address
*hv0 through hv6helper variable registershelper variables for some arithmetic operations
*rampRAM pointercontains an address pointing into the RAM
*ramvRAM valuecontains the value of the RAM element at the address currently held in ramp
*cjd_mulclock jump difference lookup multiplicitymultiplicity with which the current clk is looked up by the Op Stack Table, RAM Table, and Jump Stack Table


Register ip, the instruction pointer, contains the address of the current instruction in Program Memory. The instruction is contained in the register current instruction, or ci. Register next instruction (or argument), or nia, either contains the next instruction or the argument for the current instruction in ci. For reasons of arithmetization, ci is decomposed, giving rise to the instruction bit registers, labeled ib0 through ib7.


The stack is represented by 16 registers called stack registers (st0st15) plus the OpStack Underflow Memory. The top 16 elements of the OpStack are directly accessible, the remainder of the OpStack, i.e, the part held in OpStack Underflow Memory, is not. In order to access elements of the OpStack held in OpStack Underflow Memory, the stack has to shrink by discarding elements from the top – potentially after writing them to RAM – thus moving lower elements into the stack registers.

The stack grows upwards, in line with the metaphor that justifies the name "stack".

For reasons of arithmetization, the stack always contains a minimum of 16 elements. All these elements are initially 0. Trying to run an instruction which would result in a stack of smaller total length than 16 crashes the VM.

The registers osp and osv are not directly accessible by the program running in TritonVM. They exist only to allow efficient arithmetization.


The registers ramp and ramv are not directly accessible by the program running in TritonVM. They exist only to allow efficient arithmetization.

Helper Variables

Some instructions require helper variables in order to generate an efficient arithmetization. To this end, there are 7 helper variable registers, labeled hv0 through hv6. These registers are part of the arithmetization of the architecture, but not needed to define the instruction set.

Because they are only needed for some instructions, the helper variables are not generally defined. For instruction group stack_shrinks_and_top_3_unconstrained and its derivatives, as well as for instructions dup, swap, skiz, divine_sibling, split, and eq, the behavior is defined in the respective sections.